FIG. 1 shows a schematic and simplified cross-sectional view of an electronic integrated circuit wafer 1 comprising: a substrate 3 made of semiconductor material, a first dielectric layer 4, a second dielectric layer 5 and a passivation dielectric layer 6. Integrated on and within the substrate 3 are electronic components (such as, for example, transistor devices 3a). Integrated within the first dielectric layer 4 are conductive contacts 4a (for example, made source/drain/gate regions) and other structures (such as transistor gates 4b) surrounded by an insulating material. Integrated within the second dielectric layer 5 are metal interconnect lines 5a and metal vias 5b on a plurality of metallization levels (M1-Mn) that are surrounded by an insulating material, wherein the interconnect lines and vias are electrically connected to the contacts 4a and other structures of the first dielectric layer 4. The passivation dielectric layer 6 includes contact pads 7 which are electrically connected to the interconnect lines and vias of the second dielectric layer 5. The top surface of the passivation dielectric layer 6 is the front face of the wafer 1. The bottom surface of the substrate 3 is the back face of the wafer 1.
It is common to utilize Through-Silicon Via or Through-Semiconductor Via (collectively “TSV”) technology in the fabrication of integrated circuits. A TSV is an interconnection of conductive material that extends vertically through the integrated circuit chip so as to enable electrical connection of elements of the circuit, integrated at various levels of the structure of the integrated circuit chip, with an external face (front and/or back) of the integrated circuit. The TSV is developed vertically through the integrated circuit chip (for example, through the substrate 3 and other included layers of the wafer 1 in such a way that, at the end of the manufacturing process, the TSV is accessible from the external face of the integrated circuit chip.
FIG. 1 shows a number of examples of the use of a TSV 9. Each TSV 9 forms a conductive interconnection that extends vertically through the substrate 3 and possibly traverses (fully or partially) one or more of the layers 4, 5 and 6. In particular, by way of example, FIG. 1 shows: a TSV 9 which extends through the layer 4 and partially through the substrate 3; a TSV 9 that extends at least partially through the layer 5, through the layer 4 and partially through the substrate 3; and a TSV 9 that extends through the layers 4 and 5 and partially through the substrate 3.
For example, the TSVs 9 may be obtained as described in United States Patent Application Publication No. 2005/0101054 (incorporated by reference), or as described in “Wafer Level 3-D ICs Process Technology”, by Chuan Seng Tan, Ronald J. Gutmann and L. Rafael Reif, pp. 85-95, Springer-Verlag New York Inc. (incorporated by reference).
In the overall fabrication process, the substrate 3 with electronic components and the first dielectric layer 4 are provided through appropriate fabrication processes designated by the acronym FEOL (Front End of Line). The second dielectric layer 5 and passivation dielectric layer 6, however, are provided through appropriate fabrication processes designated by the acronym BEOL (Back End of Line). The illustration in FIG. 1 is at an intermediate stage of fabrication before the wafer is diced into individual integrated circuit chips. Thus, after the BEOL, the manufacturing process may further include the wafer dicing operation.
FIG. 2 shows the wafer 1 at a subsequent stage in the manufacturing process. Here, a step of thinning the back surface of the substrate 3 (with known techniques of lapping, or “back grinding”) of the wafer 1 has been performed to expose a portion of the back end 9b of each TSV 9. After completion of the thinning process, the substrate 3 has a reduced thickness in comparison to the intermediate stage of FIG. 1, for example a thickness of less than 100 μm.
In a next step of the manufacturing processes, the wafer 1 may be diced (for example, at the lines 10) so as to define a plurality of chips 12, each of which contains a respective electronic integrated circuit. Following dicing, the chips are packaged to form integrated circuit devices.
At the end of the manufacturing process, each TSV 9 will accordingly traverse through the entire thickness of the substrate 3 as shown in FIG. 2, providing for a direct electrical connection from the back side of the chip 12 to one or more of the included electronic components, the first dielectric layer 4, the second dielectric layer 5, and the contact pads 8. The use of TSV technology is particularly advantageous for providing three-dimensional packaging structures for the electronic integrated circuits (referred to in the art as “3D-packaging techniques” or 3D/2.5D integration techniques). In such structures, plural chips are stacked one on top of the other using the TSVs 9 to support electrical connections between the stacked chips as well as with the outside of the package.
In the light of the critical aspects of the production process, and given the nature of electrical interconnection performed by the TSVs 9, it would be advantageous to be able to verify proper TSV operation at a point of the manufacturing process preferably before performing dicing of the wafer 1. Such verification of proper TSV operation would include verification of the resistance of the path offered to the electric current circulating through the through TSVs and moreover the detection of possible leakages, defects and parasitic phenomena, for example, in regard to the substrate 3. Such TSV testing is, however, difficult at the stage of manufacturing shown in FIG. 1 because the back end 9b of each TSV 9 is still contained within the body of the substrate 3 and thus is not directly available to be probed.
U.S. Pat. No. 9,111,895 (incorporated by reference) teaches a TSV testing structure and methodology that can be used at the stage of manufacturing shown in FIG. 1. With reference to FIG. 3, the substrate 3 is doped with a first conductivity type dopant (for example, P type). The TSV 9 has its back end 9b embedded in the substrate 3. The TSV 9 is formed by a conductive region 16 (for example, made of a metal material such as copper) surrounded laterally by an insulating layer 18 (for example, made of an insulating material such as silicon oxide). A region 20 within the substrate 3 at the back end 9b of the TSV 9 is doped with a second conductivity type dopant (for example, N type). The metal material of the TSV conductive region 16 is in direct physical and electrical contact with the region 20 but is isolated from the P-type substrate 3 by the combination of the lateral insulating layer 18 and underlying N-type region 20. The N-type region 20 forms with P-type substrate 3 a PN semiconductor junction (i.e., a junction diode 22) having an anode terminal provided by the substrate 3 and a cathode terminal provided by the region 20. Electrical connection to the anode terminal is made through an electrical contact 24 made to the substrate 3 while electrical connection to the cathode terminal is made through an electrical contact 26 made to the conductive region 16 of the TSV 9. The electrical contacts 24 and 26 may be implemented, for example, using electrically conductive structures (contacts, lines, vias) present within the layers 4 and 5 as well as the pads 7 in the layer 6.
In use, the presence of the junction diode 22 at the back end 9b of the TSV 9, accessible through the electrical contacts 24 and 26 and their associated pads 7 in the layer 6, enables the electrical testing of the TSV 9 to be carried out. For example, in a test procedure a test current is circulated for application to the junction diode 22 and the test current (or corresponding voltage) is measured. More specifically, in one testing implementation the junction diode 22 is forward biased so as to enable the passage of the test current through the conductive region 16 of the TSV 9. It is thus possible to evaluate, using a test apparatus coupled to the associated pads 7, the resistance offered by TSV 9 under test to the passage of the test current. In particular, it is possible to measure a resistance of a differential type causing the test current to assume two distinct values and thus measure two corresponding differences of potential. The measured differences of potential can be evaluated to determine a fault of the TSV 9 under test. Chips with fauty TSVs 9 can be identified and then discarded following the thinning of the substrate 3 and subsequent dicing operations.
FIG. 4 shows a schematic and simplified view of the testing apparatus for performing a wafer-level testing of electrical characteristics. The wafer 1 is mounted to a chuck 30. A probe head 32 is arranged with a plurality of probes 34 can be actuated so as to approach the front face of the wafer 1 and cause the plurality of probes 34 to be placed into physical and electrical contact with the pads 7 of the wafer 1. The probe head 32 is mounted to a support 36 (for example, a printed circuit board). The probe head 32, probes 34 and support 36 form a device known to those skilled in the wafer test art as a probe card 38. FIG. 3 illustrates the physical and electrical contacting of the probes 34 with the pads 7 of the wafer 1. It is through the probes that the test current is applied and the potential measurements are made under the direction and control of connected Automated Test Equipment (ATE). As known in the art, ATE is configured to perform automatic procedures for testing and electrical sorting the various chips within the wafer 1 (before the corresponding dicing operation is performed) so as to select the chips that are operating properly for their subsequent packaging. This operation is known as “Electrical Wafer Sort” (EWS) or “Wafer Sort” (WS) and envisages execution of appropriate electrical tests on the electronic integrated circuits, and in this case the TSVs 9, in the various chips.
Although FIG. 3 illustrates a preferred implementation where the probes 34 make physical and electrical contact with the pads 7, it will be understood that in alternative implementations the probe 34 may alternatively make physical and electrical contact directly with the front end 9a of the TSVs 9. This can be accomplished, for example, in situations where the TSVs extend up to layer 6 (and are exposed through the layer 6) or in situations where testing is performed prior to BEOL processing and the formation of layers 5 and 6.
Details of possible testing scenarios, as well as other related TSV testing structures, are provided in U.S. Pat. No. 9,111,895 and will not be repeated here.